Reference is made to copending U.S. patent application Ser. No. 303,214, "Multiplexed Synchronous/Asynchronous Data Bus" filed on Jan. 27, 1989 in behalf of Wilson, et al., now U.S. Pat. No. 4,972,432, and containing related subject matter.
The present invention relates generally to data transmission systems and more particularly to a synchronous self-clocking digital data transmission system having a layered asynchronous serial digital data transmission system for increasing the rate of data transfer.
A synchronous self-clocking digital data transmission system has been described in U.S. Pat. No. 4,369,516 to Byrns. This system provides a synchronous, self-clocking, bidirectional data transmission bus which is immune to speed and timing variations and suited for data bus structures of long length. The use by a data transmitter of two bit binary states of two data signal lines enables the unique definition of the beginning and end of a data signal and the binary states of the bits of a data signal while also differentiating between addresses and data signals. A third data signal line is used by peripheral devices to return communication to the data transmitter. As implemented in some mobile and portable radiotelephone equipment currently available for cellular radiotelephone systems, the synchronous self-clocking data bus is operated at relatively low data rates. The inherent capabilities of the bus and its data rate allow operation in areas of high electrical noise (e.g. an automobile) and produces little electromagnetic interference itself.
Asynchronous serial data transmission systems are well known in the art and offer high rates of data transfer. For example, the MC68HC11A8 microprocessor utilizes a serial communications interface (SCI) whereby the microprocessor may communicate with peripheral devices using a standard NRZ (mark/space) format on both a receive data input port (RXD) and a transmit data output port (TXD). The MC68HC11A8 serial communications interface is further described in the HMOS Single Chip Microcomputer Data Book, order number ADI1207R1, 1987, pp. 5-1to 5-5.
In order to realize the features of both types of data transmission systems in the subscriber equipment of cellular radiotelephone systems, it would be necessary to incorporate both on a common physical bus structure in order to reduce the number of lines and connectors. The size of the physical bus is particularly important in portable radiotelephone equipment. It is also desirable that the self-clocking synchronous bus in current use continue in use unmodified without retrofitting equipment already in service. This desire is in conflict with the increasing necessity of exchanging data at higher transmission rates.
It would be desirable therefore, to combine the immunity to speed variations, timing variations, and long physical bus length of the present low data transfer rate synchronous data bus with the increased data transfer rate of the asynchronous data bus. Since in many applications the number of bus lines and corresponding connectors is an important consideration, it would also be desirable to maintain the number of signal lines in a combined bus structure.